1. Field of the Invention
The present invention relates to a processor including a self-diagnostic function, and in particular, to a processor, which can carry out a self-diagnosis with respect to an adder-subtracter without requiring an expected value data which evaluates a diagnostic result.
2. Description of the Related Arts
Conventionally, in a manufacture process of an integrated circuit such as a processor including a self-diagnostic function, a TAP (Test Access Port) controller is built in the integrated circuit as a self-diagnostic circuit. Further, in a wafer manufacture step and a package manufacture step, a self-diagnostic test is carried out with respect to a built-in RAM and a built-in arithmetic unit. In this manner, an integrated circuit having a manufacturing defect is found and removed, and thereafter, an integrated circuit passing the self-diagnostic test is used. By doing so, it is possible to prevent a wasteful build-up of LSI package and processor module, and thus, to improve a yield in a process after wafer manufacture.
FIG. 1 is a view showing a basic hardware configuration of a conventional processor. An instruction memory management unit (IMMU) 100 makes an exchange between a logical address and a physical address using an instruction TLB (Translation Look-aside Buffer) 102, and then, a pre-fetch unit 104 pre-fetches an instruction from an instruction cache 110 to an instruction field 106 via a branch prediction 108. Further, a secondary cache 112 is interposed between the instruction cache 110 and a processor local inter-connector 114, and is connected to an external unit via the processor local inter-connector 114. An instruction fetched from the instruction cache 110 is pre-decoded by a pre-decode unit 116, and thereafter, is stored in an instruction buffer 118. Further, a dispatch unit 120 distributes the instruction thus fetched to each of a branch unit 122, an integer arithmetic unit register file (IEU register file) 124 and a floating-point unit register file (FPU register file) 128. Following the IEU register file 124, integer arithmetic units (IE ALU) 130-1 and 130-2 are provided, and then, execute an integer operation instruction. Thereafter, these integer arithmetic units 130-1 and 130-2 output the operation result to a completion unit 134, and then, the operation result is loaded or stored according to an instruction from a load-store unit 126. Moreover, following the floating-point unit register file 128, floating-point arithmetic units (FP ALU) 132-1 and 132-2 are provided, and then, execute a floating-point operation instruction. Thereafter, these floating-point arithmetic units 132-1 and 132-2 output the operation result to the completion unit 136, and then, the operation result is loaded or stored according to an instruction from a load-store unit 126.
FIG. 2 is a view showing a basic configuration of the integer arithmetic unit including an instruction decoder in the processor shown in FIG. 1. An integer operation instruction from the dispatch unit 138 is latched by a staging latch 144, and then, is decoded by a decoder 150. A source register 140 stores a first operand of instruction; on the other hand, a source register 142 stores a second operand of instruction. The first and second operands are latched by staging latches 146 and 148, respectively, and thereafter, are inputted to an arithmetic unit (ALU) 152. Then, according to an operation instruction of addition instruction ADD or subtraction instruction SUB decoded by the decoder 150, the arithmetic unit 152 executes addition or subtraction of two input data so that the operation result is latched by a staging latch 156. The operation result of the staging latch 156 is stored in a destination register 168 via a staging latch 166 from a multiplexer 164. Operation instructions other than addition instruction ADD or subtraction instruction SUB decoded by the decoder 150 are latched by the staging latch 154, and thereafter, are given to a logical instruction unit 162. At that time, logic operations of AND, OR, NAND, NPR, XOR or XNOR are executed with respect to two data inputted from the staging latches 158 and 160. The operation result is stored in the destination register 168 via the multiplexer 164 and the staging latch 166.
The processor including the arithmetic unit as described above is mounted with a self-diagnostic circuit, which is used for an adder-subtracter as shown in FIGS. 3A and 3B provided in the arithmetic unit 152. In a wafer manufacture process and a package manufacture process, the self-diagnostic circuit carries out a self-diagnostic test with respect to a built-in arithmetic unit. FIG. 24 is a view showing a configuration of a conventional adder-subtracter circuit mounted with a self-diagnostic circuit. For example, a two-input adder-subtracter 202 with carry input Cin is mounted as a test object 200. An input side of the adder-subtracter 202 is provided with a general register file 204, selectors 210 and 212 and source registers 214 and 215. An output of the source register 215 is inputted directly to one of the selector 218 branched into two while being inverted by an inverter 216 so as to be inputted to the other of the selector 218. The selector 218 makes a changeover of addition input and subtraction input with respect to the adder-subtracter 202. The operation result of the adder-subtracter 202 is stored in the destination register 220. The addition and subtraction by the adder-subtracter 202 are carried out on the basis of the addition instruction ADD or subtraction instruction SUB of a decoder 230 decoding an operation code 232. Now, if each data of the source registers 214 and 216 are set as A and B, in the case where the addition instruction ADD is given from the decoder 230, the selector 218 selects a value B of the source register 215. Then, the selector 218 inputs the value to the adder-subtracter 202 while setting the carry input of the adder-subtracter 202 as Cin=0. Therefore, the adder-subtracter 202 executes an addition of C=A+B. Moreover, in the case where the subtraction instruction SUB is given from the decoder 230, the selector 218 selects an output of the inverter 216 inverting the value B of the source register 215. Then, the selector 218 inputs the inverted output to the adder-subtracter 202 while setting the carry input of the adder-subtracter 202 as Cin=1. Therefore, the adder-subtracter 202 executes a subtraction of C=Axe2x88x92B. In this case, the subtraction of C=Axe2x88x92B executed by the adder-subtracter 202 is carried out in the following manner. More specifically, an inverted value of B by the inverter 216 is one""s complement B1""s, and then, the carry input Cin=1 is added to the one""s complement B1""s in the adder-subtracter 202, and thereby, two""s complement B2""s is found. Further, the two""s complement B2""s is added to A, and thereby, the following subtraction C=Axe2x88x92B=A+B1""s+1=A+B2""s is carried out. A self-diagnostic controller 228 is provided as a self-diagnostic circuit with respect to the add-subtract circuit as described above. The self-diagnostic controller 228 includes a TAP (Test Access Port) controller 226 and a comparator 234.
In a processor mounted with the aforesaid self-diagnostic circuit, prior to the start of self-diagnosis, the TAP controller 226 executes the following preparation. More specifically, the TAP controller 226 reads a great many of self-diagnostic input data from the external RAM or the like, and a great many of expected value data obtained when an arithmetic unit is normally operated according to the self-diagnosis using the input data in the general register file 240. Next, the TAP controller 226 starts the self-diagnostic controller 228, and in the first cycle, reads a source data 206 used as a first operand a source data 208 used as a first operand, and an expected value 225 from the general register file 204. These source data 206 and 208 are stored in the source registers 214 and 215 via selectors 210 and 212, respectively. Moreover, the expected value 225 is set to one input of the comparator 234 of the self-diagnostic controller 228. In the next cycle, for example, two source data are added according the addition instruction ADD, and then, the addition result is stored in the destination register 220. The addition result 224 is compared with the expected value 225 already read by the comparator 234 of the self-diagnostic controller 228. In the case where the addition result and the expected value 224 correspond by the comparator 234, the arithmetic unit 202 is normal. On the other hand, in the case where the above two have no correspondence, a judgment is made such that the arithmetic unit 202 has a failure, and then, the self-diagnostic controller 228 outputs an error to the external unit so as to remove a processor causing the error from a manufacture process. The above self-diagnostic processing is carried out with respect to all input data and expected values prepared in the general register file 204. Thereafter, if a processor has no failure, the processor passes the test, and then, is transferred to the next process.
Moreover, the arithmetic circuit of FIGS. 3A and 3B is provided with linear feedback shift registers (LFSR) 236 and 238, which are operated as a pseudo-random number generator. These linear feedback shift registers set data X and Y read from the general register file 204 as initial value via the source registers 214 and 215, and thereafter, generate a pseudo-random number according to the control from the self-diagnostic controller 228, and thus, can perform a self-diagnosis. In such a self-diagnosis of generating the pseudo-random number, there is a need of preparing an expected value corresponding to a pseudo-random number generated in diagnosis, and reading the prepared expected value in the general register file 204. In this case, although preparation and read of the input data are unnecessary, an expected value is required.
However, in an integrated circuit such as the processor including the arithmetic unit as described above, in the case where the integrated circuit is mounted with a self-diagnostic function for an arithmetic unit, a large-scale and complicate self-diagnostic circuit is required resulting from the following reason. Namely, in the case of carrying out a self-diagnostic test, the following processings must be carried out. More specifically, first, there is a need of reading a great number of self-diagnostic input data and a great number of expected value data obtained when an arithmetic unit is normally operated by a self-diagnosis using the input data from the external RAM or the like. Further, there is a need of repeating processing which compares a signature register value storing the arithmetic result based on the input data with the expected value. For this reason, in the case where the integrated circuit is mounted with a self-diagnostic function for an arithmetic unit, a silicon semiconductor used as a main body of the integrated circuit is made into a small size, and the number of chips capable of being manufactured from a wafer is increased so as to improve a yield. In this case, however, the large-scale and complicate self-diagnostic circuit is mounted on the integrated circuit; for this reason, it is impossible to make small a die size. As a result, the yield is reduced. Moreover, the die size is made small so as to realize a low power consumption of processor. In this case, however, the self-diagnostic circuit is a large scale and complicate; for this reason, a problem has arisen such that it is impossible to make small the die size, and therefore, to sufficiently realize a low power consumption. In addition, in a manufacture of integrated circuit such as processor or the like, a time allocating to a self-diagnostic test per processor is determined depending upon the number of products month by month. In accordance with the allocated time, an input data and an expected value data used for self-diagnosis are remade; for this reason, a problem has arise such that much labor and time are spent for the preparation.
It is, therefore, an object of the present invention to provide a processor, which can carry out a self-diagnosis with respect to arithmetic unit using only input data without requiring an expected value data.
In order to achieve the above object, the present invention relates to a processor including a self-diagnostic function. The processor comprises: an arithmetic circuit including an adder-subtracter, which is a diagnostic object; a data store unit which stores a self-diagnostic data; and a self-diagnostic processing unit which inputs the self-diagnostic data, and carrying out diagnostic processing so that every bit of operation result become all zero xe2x80x9c0xe2x80x9d or all xe2x80x9c1xe2x80x9d by the arithmetic circuit.
According to the present invention, the arithmetic circuit and the self-diagnostic processing unit are constructed in a manner that in order to easily make a check, every bit of the operation result is all zero xe2x80x9c0xe2x80x9d (or all xe2x80x9c1xe2x80x9d) with respect to an arbitrary self-diagnostic input data. By doing so, there is no need of providing an expected value required for a conventional self-diagnosis and a comparator circuit for the expected value. Therefore, it is possible to make small a circuit scale required for realizing a self-diagnosis; as a result, a die side processor can be made small. Further, it is possible to realize an integrated circuit such as a processor mounted with a self-diagnostic function contributing to an improvement of yield of processor and low power consumption.
In this case, the self-diagnostic processing unit carries out a self-diagnosis such that the operation result by the following addition and subtraction becomes all zero xe2x80x9c0xe2x80x9d when two input data are set as X and Y.
(i) subtraction Z=Xxe2x88x92Y (X: minuend, Y: subtrahend)
(i) subtraction Zxe2x80x2=Yxe2x88x92X (Y: minuend, X: subtrahend)
(ii) addition of two subtraction results Zxe2x80x3=Zxe2x80x2+Z
(iii) If the addition result is all zero xe2x80x9c0xe2x80x9d, the adder-subtracter is normal, and if not so, the adder-subtracter has a failure.
More specifically, the arithmetic circuit includes: a first source register which stores a first operand A; a second source register which stores a second operand B; a complement circuit (inverter) which inverts the second operand B so as to output one""s (1xe2x80x2s) complement B1""s; a first adder-subtracter with carry input of being as a diagnostic object, which inputs the first operand A as a minuend and inputting the output value B1""s of the complement circuit as a subtrahend together with carry input Cin, and adds xe2x80x9c1xe2x80x9d to one""s (1xe2x80x2s) complement B1""s so as to generate two""s (2xe2x80x2s) complement B2""s, and further, adds the generated complement B2""s to the first operand A so as to carry out a subtraction C=(Axe2x88x92B); and a second adder-subtracter provided on the next stage of the first adder-subtracter.
The self-diagnostic processing unit carries out the following diagnostic processing with respect to the aforesaid arithmetic circuit using arbitrary self-diagnostic data X and Y having a predetermined bit length stored in the first and second source registers.
(i) The self-diagnostic processing unit carries out a subtraction Z=(Xxe2x88x92Y) as Z=(X+Y2""s)=(X+Y1""s+1) using the complement circuit 30 and the first adder-subtracter 12 in a first cycle.
(ii) The self-diagnostic processing unit replaces the minuend X with the subtrahend Y each other, and carries out a subtraction Zxe2x80x2=(Yxe2x88x92X) as Z=(Y+X2""s)=(Y+X1""s+1) using the complement circuit 30 and the first adder-subtracter 12 in a second cycle.
(iii) The self-diagnostic processing unit carries out an addition Zxe2x80x3 of the subtraction results Z and Zxe2x80x2 in the first and second cycles, that is, Zxe2x80x3=(Z+Zxe2x80x2)=(X+X1""s+1+Y+Y1""s +1) using the second adder-subtracter 36 in a third cycle.
(iv) The self-diagnostic processing unit makes a judgment such that the first adder-subtracter is normal in the case where every bit of the addition result is all zero xe2x80x9c0xe2x80x9d while making a judgment such that the first adder-subtracter has a failure in the case where every bit of the addition result is other than zero xe2x80x9c0xe2x80x9d.
Moreover, according to another embodiment, the self-diagnostic processing unit carries out a self-diagnosis based on the following subtraction, conversion and comparative judgment when two input data are set as X and Y.
(i) subtraction Z=Xxe2x88x92Y (X: minuend, Y: subtrahend)
(ii) subtraction Zxe2x80x2=Yxe2x88x92X (Y: minuend, X: subtrahend)
(iii) calculation of two""s (2xe2x80x2s) Z2""s with respect to the subtraction result Zxe2x80x2 Zxe2x80x22""s=Z1""s+1
(iv) comparison of the subtraction result Z with Zxe2x80x2 Z=Zxe2x80x22""s.
(v) If the comparative result is correspondent, the adder-subtracter is normal, and if not so, the adder-subtracter has a failure.
More specifically, the arithmetic circuit includes: a first source register which stores a first operand A; a second source register which stores a second operand B; a first complement circuit which inverts the second operand B so as to output one""s (1xe2x80x2s) complement B1""s; an adder-subtracter with carry input of being as a diagnostic object, which inputs the first operand A as a minuend and inputting the output value B1""s of the complement circuit as a subtrahend together with carry input Cin=1, and adds xe2x80x9c1xe2x80x9d to one""s (1xe2x80x2s) complement B1""s so as to generate two""s (2xe2x80x2s) complement B2""s, and further, adds the generated complement B2""s to the first operand A so as to carry out a subtraction C=(Axe2x88x92B); and a second complement circuit which inverts the subtraction value C of the adder-subtracter and adding xe2x80x9c1xe2x80x9d thereto so as to output two""s (2xe2x80x2s) complement C2""s; a second adder-subtracter provided on the next stage of the first adder-subtracter; and a comparator which compares an output of the adder-subtracter with an output of the second complement circuit. The self-diagnostic processing unit carries out the following diagnostic processing with respect to the aforesaid arithmetic circuit using arbitrary self-diagnostic data X and Y having a predetermined bit length stored in the first and second source registers.
(i) The self-diagnostic processing unit carries out a subtraction Z=(Xxe2x88x92Y) as Z=(X+Y2""s)=(X+Y1""s+1) using the first complement circuit and the adder-subtracter in a first cycle.
(ii) The self-diagnostic processing unit replaces the minuend X with the subtrahend Y each other, and carries out a subtraction Zxe2x80x2=(Yxe2x88x92X) as Z=(Y+X2""s)=(Y+X1""s+1) using the first complement circuit and the adder-subtracter in a second cycle, and outputs a complement Zxe2x80x22s=(Z1""s+1) of the subtraction result Zxe2x80x2 from the second complement circuit so as to compare it with the subtraction result Z of the first cycle, and makes a judgment such that the first adder-subtracter is normal in the case where the subtraction results Zxe2x80x2 and Z are correspondent (Zxe2x80x22""s=Y2""sxe2x88x92X2""s=X+Y2""s=Z) while making a judgment such that the first adder-subtracter has a failure in the case where the subtraction results Zxe2x80x2 and Z are not correspondent.
The comparator makes a judgment in the following manner. More specifically,
Zxe2x80x22""s=Y2""sxe2x88x92X2""s=X+Y2""s=Zxe2x80x83xe2x80x83(1) 
The above formation is certified in the following manner.
Z=Xxe2x88x92Y=X+Y1""s+1=X+Y2""sxe2x80x83xe2x80x83(2) 
Zxe2x80x2=Yxe2x88x92X=Y+X1""s+1=Y+X2""sxe2x80x83xe2x80x83(3) 
So, from the above equation (2),
Y2""s=xe2x88x92Yxe2x80x83xe2x80x83(4) 
From the above equation (3),
X2""s=xe2x88x92Xxe2x80x83xe2x80x83(5) 
Accordingly, when the above equations (4) and (5) are substituted for the above equation (1) and is transformed, the following equation is obtained.                                           Z            xe2x80x2                    ⁢                      2            xe2x80x2                    ⁢          s                =                                            Y2              xe2x80x2                        ⁢            s                    -                                    X2              xe2x80x2                        ⁢            s                                                  =                              -            Y                    -                      (                          -              X                        )                                                  =                              -            Y                    +          X                                        =                  X          -          Y                    
Then, when substituting the above equation (2) for the second term xe2x80x9cxe2x88x92Yxe2x80x9d of the right side,                                           Z            xe2x80x2                    ⁢                      2            xe2x80x2                    ⁢          s                =                  X          +                                    Y2              xe2x80x2                        ⁢            s                                                  =        Z            
Therefore, the relation Zxe2x80x22""s=Z shown in the above equation (1) is formed.
Various modifications may be possible with respect to the configuration of arithmetic circuit and self-diagnostic processing such that the operation result of the self-diagnosis becomes all zero xe2x80x9c0xe2x80x9d or is made correspondent.